1. Field of the Invention
This invention relates to improvements in semiconductor integrated circuit interconnection methods and products, and, more particularly, to improvements in the manufacture of integrated circuit chips employing flexible, a multilevel interconnection film and the product made by the method.
2. Description of Related Art including information disclosed under .sctn..sctn.1.97-1.99
In the past, there have been numerous techniques advanced to increase the density of integrated circuits. Among those proposed have been various interconnection schemes involving modifications to printed circuit boards, thick film hybrid circuits, flexible circuits and multilayer interconnection structures on semiconductor integrated circuits themselves.
For example, in the printed circuit board technology, single and double sided boards have been made by evaporating copper or other conductive material in a desired pattern onto a board of dielectric material, such as fiberglass, epoxy, or some combination of these or similar materials. Copper sheets have also been laminated for instance, with an appropriate heat curable adhesive, onto boards, followed by patterning the conductive leads by photoresist masking and etching techniques enabling individual component leads to be placed in through holes and wave soldered in place.
Multilayer boards have also been proposed for more complex routing of the interconnection leads, such boards being fabricated, for instance, by stacking individual boards having patterned leads and affixing them by applying and curing a heat curable adhesive to form a single laminate.
In the fabrication of thick film hybrid circuits a conductive ink is silk screened onto a ceramic substrate. The ink is converted to a metallic form by firing the inked substrate in a high temperature oven. The components are placed, held in place by a high temperature solder which is inked onto the pad areas, and which has an adhesive nature at lower temperatures. These circuits are generally designed for use at higher temperature environments, and usually, the components are not pre-packaged to protect them from moisture and other adverse chemical environments: consequently, they are often encapsulated in a hermetic package with gold plated leads for interconnection to the next level of assembly. These circuits often are prohibitively expensive.
In multilayer interconnection structures which have been used on semiconductor integrated circuits, sometimes a polyamic acid resin is spun onto a semiconductor substrate containing one or more semiconductor devices to create, after a cure cycle, a polyimide dielectric insulator. By successive coating and patterning of a metal lead level and a polyimide level with appropriate vias, it is possible to construct two or more levels of metal interconnection on integrated circuits. The interconnection provides more flexibility in connecting transistors, diodes, resistors, and other components in the semiconductor layer of the circuit, enabling higher densities to be obtained in monolithic integrated circuits. This technology forms the backbone for the manufacture of wafercast multilevel interconnection films, and is well documented in the patents of S. Harada et al.. U.S. Pat. No. 3,801,880, entitled "Multilayer Interconnected Structure for Semiconductor Integrated Circuit and Process for Manufacturing the Same", and in U.S. Pat. No. 4,040,083, entitled "Aluminum Oxide Layers Bonding Polymer Resin Layer to Semiconductor Device". Reference also made to U.S. Pat. No. 4,369,090 by the applicant hereof entitled "Process for Etching Sloped Vias in Polyimide Insulators", said application being assigned to the assignee hereof and incorporated herein by reference.